1. Field of the Invention
The present invention relates to a debugging method, and more particularly, to a debugging method executed via a scan chain for a scan test, and circuitry system related thereto.
2. Description of the Prior Art
In integrated circuit (IC) testing, different methods for controlling the number of pads being used always present an issue due to the large amount of signal lines installed in a digital/analog IC. Another important area in the field of IC testing is debugging. A frequency signal generated by a phase locked loop (PLL) of the IC may deviate from what is desired and therefore needs to be observed. In prior art solutions, the frequency signal generated by the PLL is inputted into a frequency divider, and then outputted via a pad, allowing the user to observe the frequency signal and perform debugging. When a plurality of circuits having large amount of signal lines require debugging, a large number of pads will thus be required, thus increasing the manufacturing cost.